74 series :: Ttl ics 74200 74299

TTL ICs: 74200...74299


74203

6-line inverting clock driver.
    +---+--+---+
 1Y |1  +--+ 20| 1A
 2Y |2       19| 2A
 3Y |3       18| 3A
GND |4       17|
GND |5   74  16| VCC
GND |6  203  15| VCC
GND |7       14|
 4Y |8       13| 4A
 5Y |9       12| 5A
 6Y |10      11| 6A
    +----------+

74204

6-line inverting clock driver.
    +---+--+---+
 1Y |1  +--+ 20| 1A
 2Y |2       19| 2A
 3Y |3       18| 3A
GND |4       17|
GND |5   74  16| VCC
GND |6  204  15| VCC
GND |7       14|
 4Y |8       13| 4A
 5Y |9       12| 5A
 6Y |10      11| 6A
    +----------+

74208

Dual 3-state 1-line to 4-line noninverting clock driver.
    +---+--+---+
1Y2 |1  +--+ 20| 1Y1
1Y3 |2       19| 1A
1Y4 |3       18| /1OE1
GND |4       17| /1OE2
GND |5   74  16| VCC
GND |6  208  15| VCC
GND |7       14| 2A
2Y1 |8       13| /2OE1
2Y2 |9       12| /2OE2
2Y3 |10      11| 2Y4
    +----------+

74209

Dual 3-state 1-line to 4-line noninverting clock driver.
    +---+--+---+
1Y2 |1  +--+ 20| 1Y1
1Y3 |2       19| 1A
1Y4 |3       18| /1OE1
GND |4       17| /1OE2
GND |5   74  16| VCC
GND |6  209  15| VCC
GND |7       14| 2A
2Y1 |8       13| /2OE1
2Y2 |9       12| /2OE2
2Y3 |10      11| 2Y4
    +----------+

74221

Dual monostable multivibrators with Schmitt-trigger inputs.
       +---+--+---+
  /1TR |1  +--+ 16| VCC
   1TR |2       15| 1RCext
 /1RST |3       14| 1Cext
   /1Q |4   74  13| 1Q
    2Q |5  221  12| /2Q
 2Cext |6       11| /2RST
2RCext |7       10| 2TR
   GND |8        9| /2TR
       +----------+

74237

1-of-8 noninverting decoder/demultiplexer with address latches.
     +---+--+---+
  S0 |1  +--+ 16| VCC
  S1 |2       15| Y0
  S2 |3       14| Y1
 /LE |4   74  13| Y2
/EN2 |5  237  12| Y3
 EN1 |6       11| Y4
  Y7 |7       10| Y5
 GND |8        9| Y6
     +----------+

74238

1-of-8 noninverting decoder/demultiplexer.
     +---+--+---+            +---+----+----+---+---+---*---+---+---+---+
  S0 |1  +--+ 16| VCC        |EN1|/EN2|/EN3| S2| S1| S0|/Y0|/Y1|...|/Y7|
  S1 |2       15| Y0         +===+====+====+===+===+===*===+===+===+===+
  S2 |3       14| Y1         | 0 | X  |  X | X | X | X | 0 | 0 | 0 | 0 |
/EN3 |4   74  13| Y2         | 1 | 1  |  X | X | X | X | 0 | 0 | 0 | 0 |
/EN2 |5  238  12| Y3         | 1 | 0  |  1 | X | X | X | 0 | 0 | 0 | 0 |
 EN1 |6       11| Y4         | 1 | 0  |  0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
  Y7 |7       10| Y5         | 1 | 0  |  0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
 GND |8        9| Y6         | 1 | 0  |  0 | . | . | . | 0 | 0 | . | 0 |
     +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
                             +---+----+----+---+---+---*---+---+---+---+

74239

Dual 1-of-4 noninverting decoder/demultiplexer.
     +---+--+---+            +---+---+---*---+---+---+---+
/1EN |1  +--+ 16| VCC        |/EN| S1| S0| Y0| Y1| Y2| Y3|
 1S0 |2       15| /2EN       +===+===+===*===+===+===+===+
 1S1 |3       14| 2S0        | 1 | X | X | 0 | 0 | 0 | 0 |
 1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
 1Y1 |5  239  12| 2Y0        | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
 1Y2 |6       11| 2Y1        | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
 1Y3 |7       10| 2Y2        | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
 GND |8        9| 2Y3        +---+---+---*---+---+---+---+
     +----------+

74240

Dual 4-bit 3-state inverting buffer/line driver.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A1 |2       19| /2OE
/2Y4 |3       18| /1Y1
 1A2 |4       17| 2A4
/2Y3 |5  74   16| /1Y2
 1A3 |6  240  15| 2A3
/2Y2 |7       14| /1Y3
 1A4 |8       13| 2A2
/2Y1 |9       12| /1Y4
 GND |10      11| 2A1
     +----------+

74241

Dual 4-bit 3-state noninverting buffer/line driver.
One active low, one active high output enable.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A4 |2       19| 2OE
 2Y1 |3       18| 1Y1
 1A3 |4       17| 2A4
 2Y2 |5  74   16| 1Y2
 1A2 |6  241  15| 2A3
 2Y3 |7       14| 1Y3
 1A1 |8       13| 2A2
 2Y4 |9       12| 1Y4
 GND |10      11| 2A1
     +----------+

74242

4-bit 3-state inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.
     +---+--+---+
/GAB |1  +--+ 14| VCC
     |2       13| GBA
  A1 |3  74   12|
  A2 |4  242  11| B1
  A3 |5       10| B2
  A4 |6        9| B3
 GND |7        8| B4
     +----------+

74243

4-bit 3-state noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.
     +---+--+---+
/GAB |1  +--+ 14| VCC
     |2       13| GBA
  A1 |3  74   12|
  A2 |4  243  11| B1
  A3 |5       10| B2
  A4 |6        9| B3
 GND |7        8| B4
     +----------+

74244

Dual 4-bit 3-state noninverting buffer/line driver.
     +---+--+---+
/1OE |1  +--+ 20| VCC
 1A1 |2       19| /2OE
 2Y4 |3       18| 1Y1
 1A2 |4       17| 2A4
 2Y3 |5  74   16| 1Y2
 1A3 |6  244  15| 2A3
 2Y2 |7       14| 1Y3
 1A4 |8       13| 2A2
 2Y1 |9       12| 1Y4
 GND |10      11| 2A1
     +----------+

74245

8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.
    +---+--+---+             +---+---*---+---+
DIR |1  +--+ 20| VCC         |/EN|DIR| A | B |
 A1 |2       19| /EN         +===+===*===+===+
 A2 |3       18| B1          | 1 | X | Z | Z |
 A3 |4       17| B2          | 0 | 0 | B | Z |
 A4 |5  74   16| B3          | 0 | 1 | Z | A |
 A5 |6  245  15| B4          +---+---*---+---+
 A6 |7       14| B5
 A7 |8       13| B6
 A8 |9       12| B7
GND |10      11| B8
    +----------+

74247

Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank input and output.
     +---+--+---+
  A1 |1  +--+ 16| VCC
  A2 |2       15| /YF
 /LT |3       14| /YG
/RBO |4  74   13| /YA
/RBI |5  247  12| /YB
  A3 |6       11| /YC
  A0 |7       10| /YD
 GND |8        9| /YE
     +----------+

74248

BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and output.
     +---+--+---+
  A1 |1  +--+ 16| VCC
  A2 |2       15| YF
 /LT |3       14| YG
/RBO |4  74   13| YA
/RBI |5  248  12| YB
  A3 |6       11| YC
  A0 |7       10| YD
 GND |8        9| YE
     +----------+

74251

8-to-1 line 3-state data selector/multiplexer with complementary outputs.
    +---+--+---+
 A3 |1  +--+ 16| VCC
 A2 |2       15| A4
 A1 |3       14| A5
 A0 |4   74  13| A6
  Y |5  251  12| A7
 /Y |6       11| S0
/EN |7       10| S1
GND |8        9| S2
    +----------+

74253

8-to-2 line 3-state noninverting data selector/multiplexer.
     +---+--+---+
/1EN |1  +--+ 16| VCC
  S1 |2       15| /2EN
 1A3 |3       14| S0
 1A2 |4   74  13| 2A3
 1A1 |5  253  12| 2A2
 1A0 |6       11| 2A1
  1Y |7       10| 2A0
 GND |8        9| 2Y
     +----------+

74256

2-of-8 addressable latch with reset and enable.
     +---+--+---+            +---+----*--------------------+
  S0 |1  +--+ 16| VCC        |/EN|/RST| Function           |
  S1 |2       15| /RST       +===+====*====================+
  1D |3       14| /EN        | 0 |  0 | 2-of-8 demultiplex |
 1Q0 |4  74   13| 2D         | 0 |  1 | addressable latch  |
 1Q1 |5  256  12| 2Q3        | 1 |  0 | reset              |
 1Q2 |6       11| 2Q2        | 1 |  1 | hold               |
 1Q3 |7       10| 2Q1        +---+----*--------------------+
 GND |8        9| 2Q0
     +----------+

74257

8-to-4 line 3-state noninverting data selector/multiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
 1Y |4   74  13| 4A1
2A0 |5  257  12| 4Y
2A1 |6       11| 3A0
 2Y |7       10| 3A1
GND |8        9| 3Y
    +----------+

74258

8-to-4 line 3-state inverting data selector/multiplexer.
    +---+--+---+
  S |1  +--+ 16| VCC
1A0 |2       15| /EN
1A1 |3       14| 4A0
/1Y |4   74  13| 4A1
2A0 |5  258  12| /4Y
2A1 |6       11| 3A0
/2Y |7       10| 3A1
GND |8        9| /3Y
    +----------+

74259

1-of-8 addressable latch with reset.
    +---+--+---+             +---+----*--------------------+
 S0 |1  +--+ 16| VCC         |/EN|/RST| Function           |
 S1 |2       15| /RST        +===+====*====================+
 S2 |3       14| /EN         | 0 |  0 | 1-of-8 demultiplex |
 Q0 |4   74  13| D           | 0 |  1 | addressable latch  |
 Q1 |5  259  12| Q7          | 1 |  0 | reset              |
 Q2 |6       11| Q6          | 1 |  1 | hold               |
 Q3 |7       10| Q5          +---+----*--------------------+
GND |8        9| Q4
    +----------+

74260

Dual 5-input NOR gates.
    +---+--+---+                 ___________
 1A |1  +--+ 14| VCC         Y = (A+B+C+D+E)
 1B |2       13| 2D
 1E |3   74  12| 2C
 1C |4  260  11| 2E
 1D |5       10| 2B
/1Y |6        9| 2A
GND |7        8| /2Y
    +----------+

74265

Dual buffer/inverter plus dual AND/NAND gates.
    +---+--+---+
 1A |1  +--+ 16| VCC         1Y=1A
 1Y |2       15| 4A
/1Y |3       14| 4Y          2Y=2A.2B
 2A |4   74  13| /4Y
 2B |5  265  12| 3B          3Y=3A.3B
 2Y |6       11| 3A
/2Y |7       10| 3Y          4Y=4A
GND |8        9| /3Y
    +----------+

74266

Quad 2-input open-collector XNOR gates.
    +---+--+---+             +---+---*---+          _     _ _
 1A |1  +--+ 14| VCC         | A | B |/Y |     Y = A$B = (A.B)+(A.B)
 1B |2       13| 4B          +===+===*===+
/1Y |3  74   12| 4A          | 0 | 0 | Z |
 2A |4  266  11| /4Y         | 0 | 1 | 0 |
 2B |5       10| 3B          | 1 | 0 | 0 |
/2Y |6        9| 3A          | 1 | 1 | Z |
GND |7        8| /3Y         +---+---*---+
    +----------+

74273

8-bit 3-state D flip-flop with reset.
     +---+--+---+            +----+---+---*---+
/RST |1  +--+ 20| VCC        |/RST|CLK| D | Q |
  1Q |2       19| 8Q         +====+===+===*===+
  1D |3       18| 8D         |  0 | X | X | 0 |
  2D |4       17| 7D         |  1 | / | 0 | 0 |
  2Q |5   74  16| 7Q         |  1 | / | 1 | 1 |
  3Q |6  273  15| 6Q         +----+---+---*---+
  3D |7       14| 6D
  4D |8       13| 5D
  4Q |9       12| 5Q
 GND |10      11| CLK
     +----------+

74276

Quad J-K and J-/K flip-flops with common set and reset.
      +---+--+---+
 /RST |1  +--+ 20| VCC
   1J |2       19| 4J
/1CLK |3       18| /4CLK
  /1K |4       17| 4K
   1Q |5   74  16| 4Q
   2Q |6  276  15| 3Q
  /2K |7       14| /3K
/2CLK |8       13| /3CLK
   2J |9       12| 3J
  GND |10      11| /SET
      +----------+

74279

Quad /S-/R latches.
     +---+--+---+
 /1R |1  +--+ 16| VCC
/1S1 |2       15| /4S
/1S2 |3       14| /4R
  1Q |4   74  13| 4Q
 /2R |5  279  12| /3S2
 /2S |6       11| /3S1
  2Q |7       10| /3R
 GND |8        9| 3Q
     +----------+

74280

9-bit odd/even parity generator/checker.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A8
      |3   74  12| A7
   A2 |4  280  11| A6
 EVEN |5       10| A5
  ODD |6        9| A4
  GND |7        8| A3
      +----------+

74283

4-bit binary full adder with fast carry.
    +---+--+---+
 S2 |1  +--+ 16| VCC         S=A+B+CIN
 B2 |2       15| B3
 A2 |3       14| A3
 S1 |4   74  13| S3
 A1 |5  283  12| A4
 B1 |6       11| B4
CIN |7       10| S4
GND |8        9| COUT
    +----------+

74285

4-bit binary multiplier with open-collector outputs.
    +---+--+---+
 2C |1  +--+ 16| VCC
 2B |2       15| 2D
 2A |3       14| /GA
 1D |4   74  13| /GB
 1A |5  285  12| Y0
 1B |6       11| Y1
 1C |7       10| Y2
GND |8        9| Y3
    +----------+

74286

9-bit odd/even parity generator/checker with bus driver parity I/O port.
      +---+--+---+
   A0 |1  +--+ 14| VCC
   A1 |2       13| A8
/XMIT |3   74  12| A7
   A2 |4  286  11| A6
ERROR |5       10| A5
 PI/O |6        9| A4
  GND |7        8| A3
      +----------+

74290

4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.
     +---+--+---+
SET1 |1  +--+ 14| VCC
     |2       13| RST2
SET2 |3   74  12| RST1
  Q2 |4  290  11| /CLK1
  Q1 |5       10| /CLK0
     |6        9| Q0
 GND |7        8| Q3
     +----------+

74292

15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.
     +---+--+---+
  S1 |1  +--+ 16| VCC
  S4 |2       15| S2
 TP1 |3       14| S3
CLK1 |4  74   13| TP3
CLK2 |5  292  12|
 TP2 |6       11| /RST
   Q |7       10| S0
 GND |8        9|
     +----------+

74293

4-bit asynchronous binary counter with /2 and /8 sections and reset.
     +---+--+---+
     |1  +--+ 14| VCC
     |2       13| RST2
     |3       12| RST1
  Q2 |4  74   11| /CLK1
  Q1 |5  293  10| /CLK0
     |6        9| Q0
 GND |7        8| Q3
     +----------+

74294

15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.
     +---+--+---+
  S1 |1  +--+ 16| VCC
  S0 |2       15| S2
  TP |3       14| S3
CLK1 |4  74   13|
CLK2 |5  294  12|
     |6       11| /RST
   Q |7       10|
 GND |8        9|
     +----------+

74295

4-bit 3-state negative-edge-triggered universal shift register.
       +---+--+---+
     D |1  +--+ 14| VCC
    P0 |2       13| Y0
    P1 |3       12| Y1
    P2 |4  74   11| Y2
    P3 |5  295  10| Y3
LD//SH |6        9| /CLK
   GND |7        8| OE
       +----------+

74297

Digital phase-locked loop with 4-bit counter.
      +---+--+---+
   D1 |1  +--+ 16| VCC
   D0 |2       15| D2
   EN |3       14| D3
  KCP |4  74   13| PA2
 I//D |5  297  12| ECPD
 D//U |6       11| XORPD
IDout |7       10| PB
  GND |8        9| PA1
      +----------+

74298

8-to-4 line noninverting data selector/multiplexer with output registers.
    +---+--+---+
2A1 |1  +--+ 16| VCC
2A0 |2       15| 1Q
1A0 |3       14| 2Q
1A1 |4   74  13| 3Q
3A1 |5  298  12| 4Q
4A1 |6       11| CLK
4A0 |7       10| S
GND |8        9| 3A0
    +----------+

74299

8-bit 3-state bidirectional universal shift register with asynchronous reset and with separate shift left and shift right serial inputs. Multiplexed parallel I/O.
     +---+--+---+
  S0 |1  +--+ 20| VCC
/OE1 |2       19| S1
/OE2 |3       18| D
  P6 |4       17| Q7
  P4 |5   74  16| P7
  P2 |6  299  15| P5
  P0 |7       14| P3
  Q0 |8       13| P1
/RST |9       12| CLK
 GND |10      11| L
     +----------+









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