Mnemonics Opcode

Mnemonic OpSZAPC~sDescription Notes
ACI n CE***** 7Add with Carry Immediate A=A+n+CY
ADC r 8F***** 4Add with Carry A=A+r+CY(21X)
ADC M 8E***** 7Add with Carry to Memory A=A+[HL]+CY
ADD r 87***** 4Add A=A+r (20X)
ADD M 86***** 7Add to Memory A=A+[HL]
ADI n C6***** 7Add Immediate A=A+n
ANA r A7****0 4AND Accumulator A=A&r (24X)
ANA M A6****0 7AND Accumulator and MemoryA=A&[HL]
ANI n E6**0*0 7AND Immediate A=A&n
CALL a CD-----18Call unconditional -[SP]=PC,PC=a
CC a DC----- 9Call on Carry If CY=1(18~s)
CM a FC----- 9Call on Minus If S=1 (18~s)
CMA 2F----- 4Complement Accumulator A=~A
CMC 3F----* 4Complement Carry CY=~CY
CMP r BF***** 4Compare A-r (27X)
CMP M BF***** 7Compare with Memory A-[HL]
CNC a D4----- 9Call on No Carry If CY=0(18~s)
CNZ a C4----- 9Call on No Zero If Z=0 (18~s)
CP a F4----- 9Call on Plus If S=0 (18~s)
CPE a EC----- 9Call on Parity Even If P=1 (18~s)
CPI n FE***** 7Compare Immediate A-n
CPO a E4----- 9Call on Parity Odd If P=0 (18~s)
CZ a CC----- 9Call on Zero If Z=1 (18~s)
DAA 27***** 4Decimal Adjust AccumulatorA=BCD format
DAD B 09----*10Double Add BC to HL HL=HL+BC
DAD D 19----*10Double Add DE to HL HL=HL+DE
DAD H 29----*10Double Add HL to HL HL=HL+HL
DAD SP 39----*10Double Add SP to HL HL=HL+SP
DCR r 3D****- 4Decrement r=r-1 (0X5)
DCR M 35****-10Decrement Memory [HL]=[HL]-1
DCX B 0B----- 6Decrement BC BC=BC-1
DCX D 1B----- 6Decrement DE DE=DE-1
DCX H 2B----- 6Decrement HL HL=HL-1
DCX SP 3B----- 6Decrement Stack Pointer SP=SP-1
DI F3----- 4Disable Interrupts
EI FB----- 4Enable Interrupts
HLT 76----- 5Halt
IN p DB-----10Input A=[p]
INR r 3C****- 4Increment r=r+1 (0X4)
INR M 3C****-10Increment Memory [HL]=[HL]+1
INX B 03----- 6Increment BC BC=BC+1
INX D 13----- 6Increment DE DE=DE+1
INX H 23----- 6Increment HL HL=HL+1
INX SP 33----- 6Increment Stack Pointer SP=SP+1
JMP a C3----- 7Jump unconditional PC=a
JC a DA----- 7Jump on Carry If CY=1(10~s)
JM a FA----- 7Jump on Minus If S=1 (10~s)
JNC a D2----- 7Jump on No Carry If CY=0(10~s)
JNZ a C2----- 7Jump on No Zero If Z=0 (10~s)
JP a F2----- 7Jump on Plus If S=0 (10~s)
JPE a EA----- 7Jump on Parity Even If P=1 (10~s)
JPO a E2----- 7Jump on Parity Odd If P=0 (10~s)
JZ a CA----- 7Jump on Zero If Z=1 (10~s)
LDA a 3A-----13Load Accumulator direct A=[a]
LDAX B 0A----- 7Load Accumulator indirect A=[BC]
LDAX D 1A----- 7Load Accumulator indirect A=[DE]
LHLD a 2A-----16Load HL Direct HL=[a]
LXI B,nn 01-----10Load Immediate BC BC=nn
LXI D,nn 11-----10Load Immediate DE DE=nn
LXI H,nn 21-----10Load Immediate HL HL=nn
LXI SP,nn31-----10Load Immediate Stack Ptr SP=nn
MOV r1,r27F----- 4Move register to register r1=r2 (1XX)
MOV M,r 77----- 7Move register to Memory [HL]=r (16X)
MOV r,M 7E----- 7Move Memory to register r=[HL] (1X6)
MVI r,n 3E----- 7Move Immediate r=n (0X6)
MVI M,n 36-----10Move Immediate to Memory [HL]=n
NOP 00----- 4No Operation
ORA r B7**0*0 4Inclusive OR Accumulator A=Avr (26X)
ORA M B6**0*0 7Inclusive OR Accumulator A=Av[HL]
ORI n F6**0*0 7Inclusive OR Immediate A=Avn
OUT p D3-----10Output [p]=A
PCHL E9----- 6Jump HL indirect PC=[HL]
POP B C1-----10Pop BC BC=[SP]+
POP D D1-----10Pop DE DE=[SP]+
POP H E1-----10Pop HL HL=[SP]+
POP PSW F1-----10Pop Processor Status Word {PSW,A}=[SP]+
Mnemonic OpSZAPC~sDescription Notes
PUSH B C5-----12Push BC -[SP]=BC
PUSH D D5-----12Push DE -[SP]=DE
PUSH H E5-----12Push HL -[SP]=HL
PUSH PSW F5-----12Push Processor Status Word-[SP]={PSW,A}
RAL 17----* 4Rotate Accumulator Left A={CY,A}<-
RAR 1F----* 4Rotate Accumulator Righ A=->{CY,A}
RET C9-----10Return PC=[SP]+
RC D8----- 6Return on Carry If CY=1(12~s)
RIM 20----- 4Read Interrupt Mask A=mask
RM F8----- 6Return on Minus If S=1 (12~s)
RNC D0----- 6Return on No Carry If CY=0(12~s)
RNZ C0----- 6Return on No Zero If Z=0 (12~s)
RP F0----- 6Return on Plus If S=0 (12~s)
RPE E8----- 6Return on Parity Even If P=1 (12~s)
RPO E0----- 6Return on Parity Odd If P=0 (12~s)
RZ C8----- 6Return on Zero If Z=1 (12~s)
RLC 07----* 4Rotate Left Circular A=A<-
RRC 0F----* 4Rotate Right Circular A=->A
RST z C7-----12Restart (3X7)-[SP]=PC,PC=z
SBB r 9F***** 4Subtract with Borrow A=A-r-CY
SBB M 9E***** 7Subtract with Borrow A=A-[HL]-CY
SBI n DE***** 7Subtract with Borrow ImmedA=A-n-CY
SHLD a 22-----16Store HL Direct [a]=HL
SIM 30----- 4Set Interrupt Mask mask=A
SPHL F9----- 6Move HL to SP SP=HL
STA a 32-----13Store Accumulator [a]=A
STAX B 02----- 7Store Accumulator indirect[BC]=A
STAX D 12----- 7Store Accumulator indirect[DE]=A
STC 37----1 4Set Carry CY=1
SUB r 97***** 4Subtract A=A-r (22X)
SUB M 96***** 7Subtract Memory A=A-[HL]
SUI n D6***** 7Subtract Immediate A=A-n
XCHG EB----- 4Exchange HL with DE HL<->DE
XRA r AF**0*0 4Exclusive OR Accumulator A=Axr (25X)
XRA M AE**0*0 7Exclusive OR Accumulator A=Ax[HL]
XRI n EE**0*0 7Exclusive OR Immediate A=Axn
XTHL E3-----16Exchange stack Top with HL[SP]<->HL
PSW 
-*01
Flag unaffected/affected/reset/set
S 
S
Sign (Bit 7)
Z 
 Z
Zero (Bit 6)
AC 
  A
Auxilary Carry (Bit 4)
P 
   P
Parity (Bit 2)
CY 
    C
 Carry (Bit 0)
a p Direct addressing
M z Register indirect addressing
n nn Immediate addressing
r Register addressing
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DB n(,n) Define Byte(s)
DB 'string' Define Byte ASCII character string
DS nn Define Storage Block
DW nn(,nn) Define Word(s)
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A B C D E H L Registers (8-bit)
BC DE HL Register pairs (16-bit)
PC Program Counter register (16-bit)
PSW Processor Status Word (8-bit)
SP Stack Pointer register (16-bit)
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a nn 16-bit address/data (0 to 65535)
n p 8-bit data/port (0 to 255)
r Register (X=B,C,D,E,H,L,M,A)
z Vector (X=0H,8H,10H,18H,20H,28H,30H,38H)
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+ - Arithmetic addition/subtraction
& ~ Logical AND/NOT
v x Logical inclusive/exclusive OR
<- -> Rotate left/right
<-> Exchange
[ ] Indirect addressing
[ ]+ -[ ] Indirect address auto-inc/decrement
{ } Combination operands
( X ) Octal op code where X is a 3-bit code
If ( ~s) Number of cycles if condition true

Architecture Pin Diagram
Instruction Naming Conventions:

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